Modern integrated semiconductor circuits require a multiplicity of internal voltage levels for the operation of subcircuits and individual components. The internal voltage levels are intended to have a previously defined, temporally constant value and may be either positive or negative relative to a reference potential or a ground of the integrated semiconductor circuit.
To ensure a simple voltage supply of the integrated semiconductor circuit by a single external power source, the internal voltage levels required for the operation of the subcircuits and components are generally generated from a single, preferably positive, supply voltage applied externally to the integrated semiconductor circuit.
For example, a dynamic semiconductor memory with random access, a so-called DRAM (dynamic random access memory), contains, as subcircuits and components to be operated, an array of memory cells, a plurality of word lines, a plurality of bit lines, and an address decoder for selection of one of the memory cells based on an address by selection of one of the word lines and one of the bit lines. Each of the memory cells has a selection transistor with a control terminal and a controlled path and a storage capacitor with an electrode having a capacitance with respect to a conductive plate buried in the substrate. The control terminal of the selection transistor is connected to one of the word lines and the electrode of the storage capacitor is connected to one of the bit lines via the controlled path of the selection transistor.
For operation of the dynamic semiconductor memory with random access, one or a plurality of the following internal voltage levels, in particular, are generated from an externally applied supply voltage VDD, for example, of preferably 3.3 V, an internal supply voltage of, for example, 2.5 V for supplying the address decoder, a negative substrate bias voltage VBB of, for example, −1.3 V as bias voltage for the semiconducting substrate in order to suppress leakage currents, a plate voltage VPL of, for example, 0.9 V as bias voltage for a conductive plate buried in the substrate, an equalize voltage VBLEQ of, for example, 0.9 V for setting a reference charge on a bit line, a high voltage level VBLH of, for example, 1.8 V for writing to a memory cell, a negative switch-off voltage VNWL of, for example, −0.5 V as negative bias voltage of the word lines, and a switch-on voltage VPP of, for example, 3.5 V for a word line selected by the address decoder.
After fabrication an integrated semiconductor circuit is generally subject to a comprehensive functional test under various operating conditions. For example, the functional test for a semiconductor memory with random access include selecting a memory cell based on an address, writing information items to the selected memory cell, reading information items from the selected memory cell, and comparing the written and read information items. In this case, the same memory cells are accessed in a different order, in particular, in order to find malfunctions that depend on the access order.
The operating conditions are varied while the functional test is carried out. In particular, the ambient temperature of the integrated semiconductor circuit is increased by introducing it into a furnace. Moreover, the internal voltage levels required for operation of the subcircuits and components are altered. For this purpose, the integrated semiconductor circuit is connected to an automatic test machine which sets the internal voltage levels to previously defined test values by applying test voltages to terminals provided for this. In this case, the test values for the internal voltage levels are deliberately chosen such that the integrated semiconductor circuit is exposed to a stress that has been increased in a targeted manner. However, unfavorable operating conditions may lead to undesired damage to or destruction of components due to overstress. For example, as a result of incorrect programming of the automatic test machine, internal voltage levels outside a tolerance range around an envisaged value may be generated, which leads to destruction of the integrated semiconductor circuit.
To avoid such overstress, to prevent the integrated semiconductor circuit from being destroyed as a result of an erroneous predefinition of test voltages by the automatic test machine, is desirable.